Aliasing enhanced ofdm communications

ABSTRACT

A system comprises an analog front end (AFE), an analog-to-digital converter (ADC), and alias detection circuitry. The AFE may be operable to receive an analog signal via a communication medium, wherein a first frequency band of the analog signal is occupied by an OFDM symbol and a second frequency band of the analog signal is occupied by first aliases generated during digital-to-analog conversion of the OFDM symbol. The ADC is operable to digitize the particular band of the analog signal to generate a digital signal, wherein, during the digitization, aliasing of the first aliases results in second aliases which fall into the first frequency band. The alias detection circuitry is operable to detect the second aliases in the first frequency band of the digital signal, and process the digital signal based on the detected second aliases to generate an output signal.

PRIORITY CLAIM

This application claims priority to the following application, which ishereby incorporated herein by reference:

U.S. provisional patent application 62/137,781 titled “ALIASING ENHANCEDOFDM COMMUNICATIONS” filed on Mar. 24, 2015.

BACKGROUND

Limitations and disadvantages of conventional and traditional approachesto electronic communications will become apparent to one of skill in theart, through comparison of such systems with some aspects of the presentinvention as set forth in the remainder of the present application withreference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Systems and methods are provided for aliasing enhanced OFDMcommunications, substantially as shown in and/or described in connectionwith at least one of the figures, as set forth more completely in theclaims.

These and other advantages, aspects and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a diagram of components of a transmitter in accordance with anexample implementation of this disclosure.

FIG. 2 is a diagram of components of a receiver in accordance with anexample implementation of this disclosure.

FIG. 3 is a flowchart illustrating an example process for communicationsbetween the transmitter of FIG. 1 and receiver of FIG. 2.

FIG. 4 shows example devices which communicate over a communicationmedium.

DETAILED DESCRIPTION OF THE INVENTION

Referring first to FIG. 4, there is shown a transmitter 100 whichcommunicates over medium 404 with receiver 200.

In an example implementation in which the transmitter 100 and receiver200 operate in a closed environment the medium 404 may be air/freespace. For example, the transmitter 100 and receiver 200 may reside in ashielded enclosure/housing of a computing device. As another example,the transmitter 100 and receiver 200 may reside in room or building(e.g., a data center) which is electromagnetically shielded/isolated toprevent interference from leaking into the surrounding environment.

Similarly, the medium 404 may be air/free space in an exampleimplementation in which the transmission is at sufficiently low powersuch that spectral mask requirements permit transmission of the aliasesup to f_(RF)+B. For example, the devices 100 and 200 may be broadbandnear-field communication devices which permissibly operate onfrequencies allocated for other types of communications (e.g.,frequencies allocated for television broadcast) due to the fact that thetransmit power is below the spurious emissions mask specified (e.g., byFCC or other regulatory body) for such frequencies.

In an example implementation, the medium may be a conductive/wiredmedium (e.g., coaxial cabling, twisted-pair cabling, backplane, and/orthe like). For example, the devices 100 and 200 may be devices whichcommunicate over coaxial cable used for MoCA, DOCSIS, and/or CaTV in abuilding. As another example, the device 100 may be a fiber node and thedevice 200 may be a cable modem.

In an example implementation, the medium may be fiber optic cable. Forexample, the device 100 may be a CMTS and the device 200 may be a fibernode.

Now referring to FIG. 1 is a diagram of components of a transmitter inaccordance with an example implementation of this disclosure. Theexample transmitter 100 comprises a modulator 102, an inverse discreteFourier transform (IDFT) circuit 104, a digital-to-analog converter(DAC) circuit 106, and an analog front end (AFE) circuit 108.

In operation, the modulator 102 generates modulates the Tx data onto abaseband signal. A spectral density chart 103 for an example output ofthe modulator 102 is shown, with each bin represented by adifferently-filled rectangle. The example signal comprises five binsfrom frequency f_(S)−B to frequency f_(S), where the number of fivesubcarriers/bins was chosen arbitrarily for simplicity of illustration(there may be any number of subcarriers per OFDM symbol). The IFDT 104converts the output of the modulator 102 to the time domain.

The DAC 106 then converts the digital signal to an analog representationusing a sampling clock operating at frequency f_(S). The spectraldensity chart 107 illustrates aliasing that occurs during the conversionto analog. Specifically, aliases falling at frequencies from f_(S) tof_(S)+B are shown, where B is an integer or fractional number of hertz.In an example implementation, the aliases are not filtered out. That is,in example implementations in which a baseband signal is output onto themedium 404, the frequency response of the DAC 208 and any otherdownstream circuitry between the DAC and the medium 404 has a cutofffrequency (e.g., measured as 3 dB or some other determined criteria) atleast as high as f_(S)+B. In example implementations in which thetransmitter 100 performs upconversion to frequency f_(RF) prior totransmission onto the medium 404, the DAC 106 and any other downstreambaseband components may have a cutoff frequency at least as high asf_(S)+B and any RF components of the transmitter may have a cutofffrequency at least as high as f_(RF)+B. The AFE 108 processes the DACoutput (e.g., amplifies it and upconverts it) for output onto the medium404. The spectral density chart 111 illustrates that signal 109 includesthe aliases generated by DAC 106.

FIG. 2 is a diagram of components of a receiver in accordance with anexample implementation of this disclosure. The example receiver 200depicted comprises an AFE circuit 210, a digital-to-analog converter(DAC) circuit 208, a discrete Fourier transform (DFT) circuit 206, analias detection circuit 204, and a demodulator 202.

In operation, signal 209—corresponding to signal 109 after it haspropagated over the medium 404—is processed by AFE 210 (e.g., amplifiedand downconverted, although in some instances downconversion may beunnecessary) to generate an RF analog signal which is conveyed to DAC208. The AFE 210 is configured to pass the received signal, includingthe aliases generated by DAC 106, to the DAC 208.

The ADC 208 converts the analog signal, including the aliases generatedby DAC 106 to a digital representation using a clock operating at f_(S).The spectral density graph 207 illustrates the aliasing of the aliasesfrom f_(S) to f_(S)+B back down in-band (from f_(S)−B to f_(S)) as aresult of the operation of the DAC 208.

The DFT 306 then converts the output of the DAC 208 to the frequencydomain. The in-band portion of this signal output by the DFT 206 thuscomprises the original in-band signal plus aliases that were folded backin-band by DAC 208.

The alias detection 204 circuit is operable to determine (e.g., usingknown blind source separation techniques) what these aliases are, andeither cancel them from the in-band signal, or phase correct them andadd their energy back to the in-band signal to improve the signal tonoise ratio (SNR) of the in-band signal. In this regard, each in-bandfrequency bin of the signal output by DFT 206 may be represented as:

v _(i) ^(′) =v _(i) +c _(i) v _(i)*

where v_(i) ^(′) is received value of the subcarrier having index i,v_(i) is the transmitted value of the subcarrier having index i,c_(i)v_(i)* is the alias that has folded back onto the subcarrier havingindex i, v_(i)* is the complex conjugate of v_(i), and c_(i) is acomplex value. Thus, determining c_(i) for the subcarrier having index ienables determining the alias component present in the subcarrier havingindex i. The alias component can then be cancelled and/or its energycalculated and phase corrected for adding to the in-band energy of thesubcarrier having index i.

The output 203 of the alias detection circuit 204 is thus a cleaned, orpossibly enhanced, signal suitable for demodulation. The demodulator 202may then map the symbols back to bits.

Thus, no anti-aliasing filter is required for removing the aliasesgenerated by DAC 106, no anti-aliasing filter is required for removingaliases generated by ADC 208, and the full bandwidth from f_(S)−B tof_(S) has been used for communicating data from device 100 to device200.

Although the above assumes that the sampling frequency is preciselyequal to the upper edge of the band occupied by the OFDM symbol, it may,of course be different by some tolerance (e.g., a tolerance of 10 ppm or1 ppm).

FIG. 3 is a flowchart illustrating an example process for communicationsbetween the transmitter of FIG. 1 and receiver of FIG. 2. In block 302,a digital OFDM symbol comprising a plurality of subcarriers occupying afrequency band from f_(S)−B to f_(S)+B is generated. In block 304, thedigital OFDM symbol is converted to an analog representation using a DACthat is clocked at frequency f_(S). The aliases resulting from theconversion are preserved in the analog signal. In block 306, thebaseband signal, including the aliases generated by the DAC, isupconverted to RF. In block 308, the RF signal, including theupconverted aliases, is transmitted onto the medium 404. In block 310,the RF signal, including aliases generated by the DAC, arrives at thereceiver. In block 312, the AFE of the receiver amplifies and,optionally, downconverts the received signal, including the aliasesgenerated by the DAC. In block 314, the received signal is digitized byan ADC clocked at f_(S). The result is a digital signal from f_(S)−B tof_(S)+B. During the digitizing, the aliases generated by the DAC areagain aliased such that they fold back in-band (into the subcarriersfrom f_(S)−B to f_(S)). In block 316, the output of the ADC is processedto determine the in-band alias components and either cancel them ordetermine their energy or phase correct them and add their energy backto the in-band signal (thus providing an increase in SNR). In block 318,the in-band signal is demodulated.

In accordance with an example implementation of this disclosure, asystem (e.g., receiver 200) comprises an analog front end (AFE) (e.g.,210), an analog-to-digital converter (ADC) (e.g., 208), and aliasdetection circuitry (e.g., 204). The AFE is operable to receive ananalog signal via a communication medium (e.g., 404), wherein a firstfrequency band (e.g., f_(S)−B to f_(S)) of the analog signal is occupiedby an OFDM symbol and a second frequency band (e.g., f_(S) to f_(S)+B)of the analog signal is occupied by first aliases generated duringdigital-to-analog conversion of the OFDM symbol. The ADC is operable todigitize the particular band of the analog signal to generate a digitalsignal, wherein, during the digitization, aliasing of the first aliasesresults in second aliases which fall into the first frequency band. Thealias detection circuitry is operable to detect the second aliases inthe first frequency band of the digital signal, and process the digitalsignal based on the detected second aliases to generate an outputsignal. The processing of the digital signal may comprise removal of thedetected second aliases from the first frequency band of the digitalsignal. The processing of the digital signal may comprise removal of thedetected second aliases from the first frequency band of the digitalsignal, phase adjustment of the extracted second aliases to generatephase-adjusted aliases, and addition of the phase-adjusted aliases tothe first frequency band of the digital signal. The system may comprisea demodulator operable to demodulate the output signal. The system maycomprise discrete Fourier transform (DFT) circuitry, wherein an outputof the ADC is coupled to an input of the DFT circuitry. There may be noanti-aliasing filter circuitry that operates on signals communicatedfrom the output of the ADC to the input of the DFT circuitry. The OFDMsymbol may occupy a bandwidth of B Hz (plus or minus a tolerance), thefirst frequency may band has a bandwidth of B Hz (plus or minus atolerance), and the second frequency band may have a bandwidth of B Hz(plus or minus a tolerance).

In accordance with an example implementation of this disclosure, asystem (e.g., transmitter 100) may comprise a digital-to-analogconverter (DAC) (e.g., 106) and an analog front end (AFE) (e.g., 108).The DAC is operable to convert a digital signal that comprises a digitalrepresentation of a OFDM symbol to an analog signal that comprises: (1)an analog representation of the OFDM symbol, and (2) aliases generatedduring the conversion. The digital representation of the OFDM symbolspans from f_(S)−B hertz to f_(S) hertz of the digital signal, B hertzis the bandwidth of the OFDM symbol, f_(S) hertz is the samplingfrequency of the DAC (plus or minus a tolerance). The AFE is operable toprocess the analog signal to generate an output signal comprising: (1)the analog representation of the OFDM symbol, and (2) the aliases. Thealiases may occupy B hertz of the output signal. An input of the AFE maybe coupled to the output of the DAC. The system may not comprise ananti-aliasing filter operable to perform anti-aliasing filtering ofsignals communicated from the AFE to the DAC. The analog representationof the OFDM symbol and the aliases may occupy a band of the outputsignal that ranges from f_(S)−B to f_(S)+B. The AFE may be operable toupconvert the analog signal centered at f_(RF) hertz. The analogrepresentation of the OFDM symbol and the aliases may occupy a band ofthe output signal that ranges from f_(RF)−B to f_(RF)+B.

The present invention may be realized in hardware, software, or acombination of hardware and software. The present invention may berealized in a centralized fashion in at least one computing system, orin a distributed fashion where different elements are spread acrossseveral interconnected computing systems. Any kind of computing systemor other apparatus adapted for carrying out the methods described hereinis suited. A typical combination of hardware and software may be ageneral-purpose computing system with a program or other code that, whenbeing loaded and executed, controls the computing system such that itcarries out the methods described herein. Another typical implementationmay comprise an application specific integrated circuit or chip.

The present invention may be realized in a non-transitory computerreadable medium and/or storage medium, and/or a non-transitory machinereadable medium and/or storage medium, having stored thereon, a machinecode and/or a computer program having at least one code sectionexecutable by a machine and/or a computer, thereby causing the machineand/or computer to perform the processes as described herein.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

As utilized herein the terms “circuits” and “circuitry” refer tophysical electronic components (i.e. hardware) and any software and/orfirmware (“code”) which may configure the hardware, be executed by thehardware, and or otherwise be associated with the hardware. As usedherein, for example, a particular processor and memory may comprise afirst “circuit” when executing a first one or more lines of code and maycomprise a second “circuit” when executing a second one or more lines ofcode. As utilized herein, “and/or” means any one or more of the items inthe list joined by “and/or”. As an example, “x and/or y” means anyelement of the three-element set {(x), (y), (x, y)}. In other words, “xand/or y” means “one or both of x and y”. As another example, “x, y,and/or z” means any element of the seven-element set { (x), (y), (z),(x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z”means “one or more of x, y and z”. As utilized herein, the terms “e.g.,”and “for example” set off lists of one or more non-limiting examples,instances, or illustrations. As utilized herein, circuitry is “operable”to perform a function whenever the circuitry comprises the necessaryhardware and code (if any is necessary) to perform the function,regardless of whether performance of the function is disabled or notenabled (e.g., by a user-configurable setting, factory trim, etc.).

What is claimed is: 1-20. (canceled)
 21. A system comprising: ananalog-to-digital converter (ADC) configured to digitize an analogsignal to generate a digital signal, wherein: the analog signal isgenerated by a digital-to-analog converter (DAC), the analog signalcomprises a first alias in a first frequency band, the digital signalcomprises a second alias in the second frequency band, and the secondalias is an artifact of the first alias; and an alias detectorconfigured to process the digital signal according to a detection of thesecond alias.
 22. The system of claim 21, wherein the processing of thedigital signal comprises removal of the detected second alias from thesecond frequency band of the digital signal.
 23. The system of claim 21,wherein the processing of the digital signal comprises: removal of thedetected second alias from the second frequency band of the digitalsignal; phase adjustment of the detected second alias to generate aphase-adjusted alias; and addition of the phase-adjusted alias to thedigital signal.
 24. The system of claim 23, wherein the system comprisesa demodulator configured to demodulate the processed digital signal. 25.The system of claim 21, wherein the system comprises a discrete Fouriertransform (DFT) circuit, and wherein an output of the ADC is coupled toan input of the DFT circuit.
 26. The system of claim 25, wherein ananti-aliasing filter operates on signals communicated from the output ofthe ADC to the input of the DFT circuit.
 27. The system of claim 21,wherein a desired signal occupies a bandwidth that is equal to abandwidth of the first frequency band and a bandwidth of the secondfrequency band.
 28. A method comprising: receiving, via a communicationmedium, an analog signal, wherein a first frequency band of the analogsignal is occupied by a first alias generated during digital-to-analogconversion of a desired signal, and wherein the desired signal comprisesa plurality of subcarriers; digitizing, by an analog-to-digitalconverter (ADC), a particular band of the received signal to generate adigital signal, wherein, during the digitizing, aliasing of the firstalias results in a second alias which fall into a second frequency band;detecting, by alias detection circuitry, the second alias in the secondfrequency band of the digital signal; and processing, by the aliasdetection circuitry, the digital signal based on the detected secondalias, wherein the processing results in an output signal.
 29. Themethod of claim 28, wherein the processing of the digital signalcomprises removing the detected second alias from the digital signal.30. The method of claim 28, wherein the processing of the digital signalcomprises: removing the detected second alias from the digital signal;phase adjusting the detected second alias to generate a phase-adjustedalias; and adding the phase-adjusted alias to the digital signal. 31.The method of claim 30, comprising demodulating, by a demodulator, theoutput signal.
 32. The method of claim 28, wherein an output of the ADCis coupled to an input of a discrete Fourier transform (DFT) circuit.33. The method of claim 32, wherein anti-aliasing filtering is performedon signals communicated from the output of the ADC to the input of theDFT circuit.
 34. The method of claim 28, wherein a desired signaloccupies a bandwidth that is equal to a bandwidth of the first frequencyband and a bandwidth of the second frequency band.
 35. A systemcomprising: a digital-to-analog converter (DAC) configured to convert adigital signal that comprises a digital representation of an OrthogonalFrequency Division Multiplexing (OFDM) symbol to an analog signal thatcomprises an analog representation of the OFDM symbol and an aliasgenerated during the conversion, wherein the digital representation ofthe OFDM symbol occupies spectrum below a sample frequency of the DAC.36. The system of claim 35, wherein the alias occupies the samebandwidth as the OFDM symbol.
 37. The system of claim 35, wherein anoutput of the DAC is coupled to a transmitter.
 38. The system of claim35, wherein the analog representation of the OFDM symbol and the aliasoccupy a band of the output signal that is twice the bandwidth of theOFDM symbol.
 39. The system of claim 35, wherein the transmitter isconfigured to up-convert the analog signal to a frequency band centeredat a transmission frequency.
 40. The system of claim 35, wherein theanalog representation of the OFDM symbol and the alias occupy a band ofthe output signal that is twice the bandwidth of the OFDM symbol and iscentered on a transmission frequency.